1. Technical Field
Embodiments of the present disclosure may generally relate to an E-fuse circuit, and more particularly to a technology for processing a failed part of the E-fuse circuit.
2. Related Art
A Dynamic Random Access Memory (DRAM) is constructed by a plurality of memory cells. The plurality of memory cells are arranged in the form of a matrix. If a fail occurs even in one memory cell among a plurality of memory cells, a semiconductor memory device is sorted out as a bad product since it cannot properly perform a certain operation. The probability of a failed cell occurring increases with higher degrees of integration and higher operation speeds within a semiconductor memory device.
Therefore, a yield that is defined as the ratio of the number of good chips to the total number of chips and serves to determine a manufacturing cost is likely to decrease. Thus, research is being performed for finding not only new methods related to obtaining higher degrees of integration and higher operating speeds for a semiconductor memory devices but also for methods for efficiently repairing a failed cell to try and increase a yield.
As a method for repairing a failed cell, a technology of building in a repair circuit for replacing a failed cell with a redundancy cell is being used. In general, a repair circuit consists of redundancy columns/rows which are arranged in columns and rows each constructed by redundancy memory cells. A redundancy column/row is selected instead of a column/row in which a fail has occurred.
That is to say, if a row and/or column address signal which designates a failed cell is input, a redundancy column/row is selected instead of a failed column/row of a normal memory cell bank.
Generally, in order to represent an address which designates a failed cell, a plurality of fuses to be cut is disposed. The address of the failed cell is programmed as the plurality of fuses are selectively cut.